1. Field of Invention
The present invention relates to integrated circuits and more specifically to charge pump circuits providing high output voltage and current at low power supply voltages.
2. Description of Related Art
A charge pump is widely used in semiconductor memories, and in particular non-volatile Electrically Erasable and Programmable Read Only Memories (EEPROM) where a voltage larger than the supplied chip voltages, such as 3.3V, 2.5V is generally required up to 10V or more. These high voltages are typically not available on the chip so they are generated from the low supplied voltage. These higher voltages are mainly required in such operations as programming and erase of a memory cell. As the power supply voltage to the chip is reduced down in the range of 1.2 to 1.8 volts and below as seen in recent mobile applications, voltages higher than the power supply voltage may be required for read operations of non-volatile memories to maintain read performance. Thus there is an increasing demand for low voltage driven charge pumps that can produce a high output voltage and current.
U.S. Pat. No. 6,418,040 B1 (Meng) is directed to a cross coupled charge pump that can provide a high positive or negative or negative output voltage depending upon which state the two input voltages of the charge pump are used. In U.S. Pat. No. 6,212,107 B1 (Tsukada) a charge pump is directed to providing a stepped voltage and includes a leakage current suppression circuit. U.S. Pat. No. 6,130,574 is directed to providing a negative voltage charge pump, wherein each stage contains three or four MOS transistors and has two clocks operating at different phases. U.S. Pat. No. 6,046,625 is directed to providing a charge pump circuit having multiple mirrored stages that are controlled by logic circuitry that receives a clock signal and an enable signal. In U.S. Pat. No. 5,925,905 (Hanneberg et al.) a MOS circuit configuration is directed to a high voltage charge pump without using deep insulating wells. In U.S. Pat. No. 5,815,026 a charge pump circuit is directed to providing a high voltage low current at a high efficiency.
A conventional charge pump circuit based on a diode structure is discussed in “On-Chip High-Voltage Generation in NMOS Integrated Circuits Using Improved Voltage Multiplier Technique”, IEEE Journal of Solid-State Circuits, Vol. 11, No. 3, June 1976, pp 374-378. As shown in FIG. 1, the charge pump includes a plurality of pumping stages that are serially connected between supply voltage VDD and the output voltage Vpp. The supply voltage VDD is connected through a source device Ma to the series connections of charge transfer MOS devices Mb, which produce a high voltage output Vpp. The substrate regions of the charge transfer MOS devices Mb are held at ground. Each stage is clocked through a storage capacitor C with a clock signal P1 or P2 that are at a different phase as shown in FIG. 2. Each of these clock signals provides a high level of VDD power supply voltage and a low level of ground. The clocks are phased such that charge is transferred to the output of the first stage while the second stage is held off and then the first stage is held off while the charge from the first stage is clocked to output of the second stage. This alternate clocking of adjacent stages continues through the remainder of the serially connected charge pump circuit. The technique of prior art has been widely used, but suffers from degradation in threshold voltage of charge transfer MOS devices during its operation. The voltage between the source and substrate regions of each charge transfer MOS device Mb gradually increases during operation, which results in increasing of the effective threshold voltage of the charge transfer MOS devices Mb in each pump stage. This effect is often referred to as ‘Body effect’.
In general, the output voltage of conventional charge pump circuit, Vout can be expressed as,   Vout  =      VDD    -                  V        th            ⁡              (                  V          sb                )              +                  ∑                  i          =          1                N            ⁢                           ⁢              [                              α            ⁢                                                   ⁢            VDD                    -                                    V              th                        ⁡                          (                              V                sb                            )                                      ]            where Vth(Vsb) is threshold voltage of MOS device including body effect, VDD is power supply voltage, and N is number of stages. The α is boost coupling ratio at each node and can be given by   α  =      (                  C        b                              C          b                +                  C          p                      )  where Cb and Cp are boost coupling capacitance and stray parasitic capacitance, respectively. As a result the maximum output voltage of the conventional charge pump circuit is limited and the efficiency decreases as the number of stages increase, especially for low power supply voltage.
New techniques have been proposed to overcome the problems of the conventional charge pump circuit. A representative charge pump circuit of prior art using a four-phase clock scheme which is described in “A 5V Only 0.6 um Flash EEPROM with Row Decoder Scheme in Triple Well Structure”, IEEE Journal of Solid State Circuits, Vol. 27, No. 11, November 1992, pp 1540-1545, is shown in FIG. 3. The charge pump circuit includes a number of stages of a charge transfer MOS device Mt and an auxiliary MOS device Mg which is used to precharge the gate terminal of the charge transfer MOS device Mt for high boosting gate effect. The substrate regions of the charge transfer MOS devices Mt are held at ground. A supply voltage VDD is applied to a drain of a charge transfer MOS device Mt and an auxiliary MOS device Mg in the first stage. In subsequent stages the output of the previous stage is connected to the source of the charge transfer device Mt, the auxiliary MOS device Mg. There are two capacitors in each stage Cg and Cb, which are connected to different clocks, P2 and P3 for the first stage and P4 and P1 for the second stage. The four individual clocks, P1, P2, P3, and P4 are shown in FIG. 4. The clocks are phased such that charge is transferred to the output of the first stage wile the second stage is held off and then the first stage is held off while the charge from the first stage is clocked to output of the second stage. This alternate clocking of adjacent stages continues through the remainder of the serially connected charge pump circuit.
A prior art charge pump circuit using a floating well is described in U.S. Pat. No. 5,986,947 (Choi et al.). The charge pump circuits using a triple well P-N junction and MOS diodes are disclosed in “A 3.3V only 16 Mb DINOR flash memory”, IEEE International Solid State Circuits Conference, Digest of Technical Papers, 1995, pp 122-123, and in U.S. Pat. No. 6,100,557 (Hung et al.), respectively. The triple well charge pump provides greater efficiency with increased suppression of the body effect over other prior art. This improvement is due to the extra diode inherently formed between the well and the source of the charge transfer MOS device that can help increase the forward conduction current.
In FIG. 5 is shown a diagram of a cross sectional view of a charge pump circuit of prior art in a triple well. The drain of the charge transfer MOS device Mt is connected to the P-well and the deep N-well. This allows a parasitic capacitor between the P-well and the deep N-well and a parasitic capacitor between the deep N-well and the P-substrate. The P-well and the deep N-well consume more silicon area than the charge transfer MOS device creating large junction capacitors and diodes. There are two more parasitic diodes formed at the junctions of the source and drain of the charge transfer MOSFET device and the P-well. These diodes are much smaller that than those of the P-well to deep N-well and deep N-well and the P-substrate and are omitted from the diagrams. The diodes for the P-well and the deep N-well, Dpw and Dnw, are shown in the schematic of FIG. 6.
The parasitic capacitance of the P-well and the deep N-well negatively affects the boosting voltage coupled to the drain of the charge transfer MOS device when the boosting clock signal is on. The parasitic diodes Dpw and Dnw provide a reverse bias leakage current form the drain node of the charge transfer MOS device to the P-substrate that is connected to ground. These two effects cause a degradation of efficiency of the charge pump circuit, especially at low power supply voltages. Since th parasitic junction capacitance and the leakage current of the parasitic diode are layout dependent, the output characteristics of the conventional triple-well charge pump circuit is easily affected by layout and process variations.